1. Field of the Invention
This invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to a semiconductor device with an improved electrode structure and a method of manufacturing the same.
2. Description of the Prior Art
A prior art example of the method of manufacturing an electrode structure in a semiconductor device is shown in Japanese Laid-Open Patent Publication No. 2-303165. FIGS. 36(a) and 36(d) illustrate the process of manufacture in this prior art example.
First, as shown in FIG. 36(a), a thermal oxide film 72 is formed on a silicon substrate 71, and further, an organic resist film 73 is formed on the thermal oxide film 72 in an active region (a thin portion constituting a gate oxide film) 72a. The resist film 73 thus formed has an edge 73a extending on the active region 72a. Subsequently, as shown in FIG. 36(b), a polycrystalline silicon film 74 is formed to cover the entire upper surface of the wafer shown in FIG. 36(a). Then, as shown in FIG. 36(c), a portion of the polycrystalline silicon film 74 other than a portion covering the edge 73a of the organic resist film 73 is removed by anisotropic dry etching. Subsequently, as shown in FIG. 36(d), the organic resist film 73 is removed by isotropic dry etching.
As a result, a thin conductive film 74 is formed within the active region 72a. This conductive film 74 can be used as a gate electrode. With the MOS FET thus produced, a gate length is constituted by the thickness of the polycrystalline silicon film 74, and thus it can be extremely reduced.
In the above prior art example shown in FIGS. 36(a) to 36(d), the polycrystalline silicon film 74 which extends substantially at right angles to the semiconductor substrate surface is used as the gate electrode, and thus, the gate length is constituted by the thickness of the polycrystalline silicon film 74. It is thus possible to extremely reduce the gate length. On the demerit side, however, because of the thin gate electrode, the resistance thereof in the width direction (i.e., direction W in the drawing) is increased. For example, when the polycrystalline silicon film 74 is connected to an external electrode provided for a gate on the outer side of the active region 72a, an intended potential can not be obtained on a portion of the gate electrode which is remote from the external electrode, and therefore, the MOS transistor operation is unstable.